1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device. More particularly, the present invention relates to a split-gate nonvolatile semiconductor memory device.
2. Description of Related Art
Transistors having a split-gate structure are known as one type of device applied to an electrically erasable programmable ROM (EEPROM). FIG. 4 is a plan view schematically showing an example of a typical semiconductor device including nonvolatile semiconductor memory devices having a split-gate structure. FIG. 5 is a cross-sectional view along the line Bxe2x80x94B shown in FIG. 4.
This semiconductor device includes nonvolatile semiconductor memory devices 300 having a split-gate structure (hereinafter called xe2x80x9cmemory transistorxe2x80x9d). A memory cell array is formed by the memory transistor 300. The memory transistors 300 are arrayed in the Xxe2x80x2 direction (row direction) and the Yxe2x80x2 direction (column direction) and isolated from one another by element isolation regions 118.
Taking an N-type transistor as an example, the memory transistor 300 has a source region 114 and a drain region 116 formed of N+-type impurity diffusion layers which are formed in a P-type silicon substrate 10, and a gate insulating layer 70 formed on the silicon substrate 10, as shown in FIG. 5. A floating gate 72, a tunnel insulating layer 126, and a control gate 128 are formed on the gate insulating layer 70 in that order.
The floating gate 72 is independently disposed in each memory cell. The N-type source region 114 formed in the silicon substrate 10 is disposed between the floating gates 72 of the memory transistors 300 adjacent in the Yxe2x80x2 direction. The N-type drain region 116 formed in the silicon substrate 10 is formed between two adjacent control gates 128. Upper insulating layers 74 are formed on the floating gates 72.
Operation of the split-gate memory transistor 300 is as follows. In the case of a data write operation, channel current is caused to flow between the source region 114 and the drain region 116, thereby injecting electric charges (hot electrons) into the floating gate 72. In the case of a data erase operation, a high voltage at a predetermined level is applied to the control gate 128, whereby the electric charges stored in the floating gate 72 are transferred to the control gate 128 through the tunnel insulating layer 126 by Fowler-Nordheim tunneling (FN tunneling).
In the case of a data read operation, the potential of the drain region 116 is set higher than that of the source region 114 to apply a predetermined voltage to the control gate 128, thereby determining written data by the presence or absence of formation of the channel. Specifically, if the electric charges are injected into the floating gate 72, a channel is not formed and current does not flow since the potential of the floating gate 72 becomes lower. On the contrary, if the electric charges are not injected into the floating gate 72, since the potential of the floating gate 72 becomes higher, a channel is formed and current flows. Data stored in the memory transistor 300 can be read out by detecting a current (cell current) flowing from the drain region 116 using a sense amplifier (not shown).
At present, an increase in the speed and integration of nonvolatile semiconductor memory devices is strongly demanded. As a method of increasing the speed and integration of nonvolatile semiconductor memory devices, there is a method of increasing the cell current flowing through each memory cell, thereby reducing the period of time for detecting the cell current using the sense amplifier. This enables data stored in the memory cell to be read out at higher speed.
For example, the semiconductor device shown in FIG. 4 is provided with the floating gates 72 of which the planar configuration is elliptical. In this case, the cell current can be increased by reducing the length L1 of the axis (minor axis) of the floating gate 72 in the planar configuration in the direction parallel to the Yxe2x80x2 direction, or increasing the length L2 of the axis (major axis) of the floating gate 72 in the planar configuration in the direction parallel to the Xxe2x80x2 direction.
However, reducing the length L1 of the minor axis causes the withstanding voltage between the source region 114 and the drain region 116 to be insufficient, whereby punch-through may occur.
On the other hand, increasing the length L2 of the major axis results in an increase in the size of the planar configuration of the floating gate 72. As a result, an increase in the memory cell size is inevitable, thereby hindering higher device integration.
An object of the present invention is to provide a semiconductor device including nonvolatile semiconductor memory devices capable of an increase in the speed without increase in the memory cell size.
A semiconductor device of the present invention comprises a memory cell array in which a plurality of nonvolatile semiconductor memory devices are arrayed in a row direction and a column direction,
wherein each of the nonvolatile semiconductor memory devices includes:
a semiconductor substrate;
a floating gate disposed on the semiconductor substrate through a first insulating layer which is capable of functioning as a gate insulating layer interposed therebetween;
a second insulating layer disposed on the floating gate;
a third insulating layer which is formed in contact with at least part of the floating gate and is capable of functioning as a tunnel insulating layer;
a control gate which is isolated from the floating gate by the third insulating layer and extends in the row direction; and
impurity diffusion layers which are formed in the semiconductor substrate, forming a source region and a drain region,
wherein the nonvolatile semiconductor memory devices which are adjacent to each other in the row direction are isolated by element isolations region extending in the column direction, and
wherein one of angles formed where a major axis direction of the floating gates in a planar configuration of the memory cell array intersects the column direction is an acute angle.
The major axis direction is preferably the same as the row direction which is one of the directions in which the nonvolatile semiconductor memory devices are arrayed.
In a typical semiconductor device shown in FIGS. 4 and 5, a plurality of nonvolatile semiconductor memory devices are arrayed in the column direction and in the row direction which intersect at right angles.
In the semiconductor device of the present invention, one of the angles formed where the major axis direction intersects the column direction is an acute angle. Specifically, the one of the angles formed where the column direction intersects the row direction is an acute angle, and the floating gate may be formed so that the major axis direction is substantially parallel to the row direction. Because of this, cell current can be increased without increasing the memory cell size. This enables the speed of the nonvolatile semiconductor memory devices to be increased.
A longitudinal direction of each of the element isolation regions in the planar configuration of the memory cell array may be substantially parallel to the column direction. The longitudinal direction of the element isolation region in the planar configuration refers to the direction in which the element isolation regions extend on the semiconductor substrate for insulating the nonvolatile semiconductor memory devices adjacent in the row direction from each other.
It is preferable that, each of the element isolation regions is separately formed by every two rows of the nonvolatile semiconductor memory devices, one impurity diffusion layer which forms the source region or the drain region is separated in the row direction by the element isolation region, and the other the impurity diffusion layer which forms the drain region or the source region is formed continuously in the row direction. In this case, the other impurity diffusion layer may extend in the row direction.